Charge compensation semiconductor devices

US10651271B2 · kind B2 · utility

Assignee

• Infineon Technologies Austria AG · AT

Inventors

• Daniel Tutuc · Finkenstein, AT
• Christian Fachmann · Graz, AT
• Franz Hirler · Isen, DE
• Maximilian Treiber · Munich, DE

Key dates

• Filing date: Dec 11, 2018
• Grant date: May 12, 2020
• Expiry date: Dec 11, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/324
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for forming a field-effect semiconductor device includes providing a wafer having a substantially compensated semiconductor layer extending to an upper side and including a semiconductor material which is co-doped with n-type dopants and p-type dopants. A peripheral area laterally surrounding an active area are defined in the wafer. Trenches in the active area are filled with a substantially intrinsic semiconductor material. More p-type dopants than n-type dopants are diffused from the compensated semiconductor layer into the intrinsic semiconductor material to form a plurality of p-type compensation regions in the trenches which are separated from each other by respective n-type drift portions. P-type dopants are introduced at least into a semiconductor zone of the peripheral area, so that the semiconductor zone and a dielectric layer on the upper side form an interface. A horizontal extension of the interface is larger than a vertical extension of the trenches.