Memory devices and methods of forming the same
US10651380B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2019 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Jan 29, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
In a non-limiting embodiment, a device may be formed having a substrate that has at least a first region. A base dielectric layer is arranged over the substrate. The base dielectric layer includes an interconnect in the first region. A first electrode is arranged over the interconnect in the first region. A mask structure is arranged over the first electrode. At least one spacer stack is arranged at least partially around the mask structure and the first electrode. The spacer stack(s) includes a resistive switching element at least partially lining sidewalls of the mask structure and the first electrode, and a second electrode arranged over the resistive switching element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.