Failure detection for wire bonding in semiconductors
US10656204B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2018 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Nov 12, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N20/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a system and method for collecting trace data of integrated circuits from the back-end assembly tools and using yield, reliability, and burn-in data to distinguish good circuit traces from bad ones. Described further is an system and method for implementing a heuristic mapping of trace data for distinguishing between good or bad traces in an Internet-based or offline application. The result of this detection can then be used for yield improvement or for burn-in reduction where for example burn-in chips having “good” circuit traces are subjected to thermal stress for less time than for chips identified as having “bad” circuit traces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.