Memory die having wafer warpage reduction through stress balancing employing rotated three-dimensional memory arrays and method of making the same
US10658381B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2019 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Mar 28, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory dies on a wafer may include multiple memory blocks including bit lines extending along different directions. A memory die may include a first-type plane including first memory blocks and a second-type plane including second memory blocks. In this case, memory blocks having different bit line directions may be formed within a same memory die. An exposure field may include multiple types of memory dies that are oriented in different orientations. The bit line directions may be oriented differently in the multiple types of memory dies. Each lithographic exposure process may include a first step in which lithographic patterns in first exposure fields are oriented in one direction, and a second step in which lithographic patterns in second exposure fields are oriented in another direction. The different orientations of bit lines and word lines may change local directions of stress to reduce wafer distortion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.