Alignment through topography on intermediate component for memory device patterning
US10658589B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2018 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Jun 27, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54426
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An intermediate semiconductor device structure includes a first area including a memory stack area and a second area including an alignment mark area. The intermediate structure includes a metal interconnect arranged on a substrate in the first area and a first electrode layer arranged on the metal interconnect in the first area, and in the second area. The intermediate structure includes an alignment assisting marker arranged in the second area. The intermediate structure includes a dielectric layer and a second electrode layer arranged on the alignment assisting marker in the second area and on the metal interconnect in the first area. The intermediate structure includes a hard mask layer arranged on the second electrode area. The hard mask layer provides a raised area of topography over the alignment assisting marker. The intermediate structure includes a resist arranged on the hard mask layer in the first area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.