Systems and methods involving lock loop circuits, distributed duty cycle correction loop circuitry
US10659058B1 · kind B1 · utility
24Cited by
6References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2016 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Jun 27, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method and circuits are described that pertain to locked loop circuits, distributed duty cycle correction loop circuitry. In some embodiments, the system and circuit may involve or be configured for coupling with lock loop circuitry such as phase locked loop (PLL) circuitry and/or a delay locked loop (DLL) circuitry. For example, one illustrative implementation may include or involve a phase locked loop (PLL) with distributed duty cycle correction loop/circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.