Write level initialization synchronization
US10664173B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2018 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Apr 20, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques provided herein compensate for an internal and external timing skew between a data strobe (DQS) and a clock (CLK), by: executing at least one write leveling initialization procedure (WLInit) that uses a mode-register-write (MRW) command to synchronize a timing between a data strobe (DQS) with a clock (CLK) based upon capture of an internal write command. Internal and external timing skew is identified based upon the WLInit. The internal timing skew is skew caused internal to a memory device and the external timing skew is skew caused external to the memory device. A timing between the DQS and the CLK is adjusted based upon the internal and external timing skew.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.