Methods of semiconductor device fabrication
US10665500B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2019 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Mar 13, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/35
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure provide a method for manufacturing a semiconductor device. A first structure of first stacked insulating layers including a first via over a contact region is formed. A second structure is formed by filling at least a top region of the first via with a sacrificial layer. A third structure including the second structure and second stacked insulating layers stacked above the second structure is formed. The third structure further includes a second via aligned with the first via and extending through the second stacked insulating layers. A fourth structure is formed by removing the sacrificial layer to form an extended via including the first via and the second via. A plurality of weights associated with the first structure, the second structure, the third structure, and the fourth structure is determined, and a quality of the extended via is determined based on the plurality of weights.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.