Patent · US Active

Package including an integrated routing layer and a molded routing layer

US10665522B2 · kind B2 · utility

2Cited by

6References

13Claims

0Family size

Assignee

Intel IP Corporation · US

Inventors

Lizabeth Keser · Chandler, US
Thomas Ort · Veitsbronn, DE
Thomas Wagner · Regelsbach, DE
Bernd Waidhas · Nittendorf, DE

Key dates

Filing date	Dec 22, 2017
Grant date	May 26, 2020
Priority date	—
Expiry date	Dec 22, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/18162
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.