Package assembly
US10665565B2 · kind B2 · utility
0Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2018 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Dec 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/2076
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a bump structure disposed on a first substrate and a molding compound in physical contact with the bump structure. The bump structure protrudes from the molding compound. A conductive region is on a second substrate and contacts the bump structure. A no-flow underfill (NUF) material is vertically between the molding compound and the second substrate and laterally surrounds the bump structure. The NUF material is separated from the molding compound.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.