Method of manufacturing semiconductor package structure
US10665582B2 · kind B2 · utility
2Cited by
16References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2018 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Mar 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor package structure includes the following steps. A die is bonded to a wafer. A dielectric material layer is formed on the wafer and the die. The dielectric material layer covers a top surface and sidewalls of the die. At least one planarization process is performed to remove a portion of the dielectric material layer and a portion of the die, such that the top surface of the die is exposed and a dielectric layer aside the die is formed. The dielectric layer surrounds and covers the sidewalls of the die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.