Memory device and operation method thereof
US10666467B2 · kind B2 · utility
1Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2018 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Aug 22, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes memory cell array including a plurality of memory cells that store data, a first transmitter that transmits the data to an external device through a first data line, and a ZQ controller that performs a ZQ calibration operation to generate a first ZQ code for impedance matching of the first data line. The first transmitter encodes the first ZQ code and the first data based on a first clock and drives the first data line based on the encoded result based on a second clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.