Patent · US Active

Framework for reusing cores in simulation

US10671785B1 · kind B1 · utility

8Cited by

3References

20Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Valeria Mihalache · Santa Clara, US
Kumar Deepak · San Jose, US
Saikat Bandyopadhyay · Sherghati, IN
Sandeep S. Deshpande · Longmont, US
Feng Cai · Shanghai, CN

Key dates

Filing date	Dec 6, 2016
Grant date	Jun 2, 2020
Priority date	—
Expiry date	Mar 19, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/367
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Simulating a hardware description language design including a core and a testbench can include performing, using a processor, a first compilation of the hardware description language design by generating a compiled core unit for the core, a compiled testbench for the testbench, and synchronization data describing signals crossing a compile checkpoint boundary. A subsequent compilation of the hardware description language design can be performed by reusing the compiled core unit from the first compilation and generating a new compiled testbench for the testbench using the synchronization data.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.