Editing of layout designs for fixing DRC violations
US10671793B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2018 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | Jul 31, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present embodiments relate to providing an overlap view of external and internal components of all instance circuit cells related to a master circuit cell in a same layout view. A layout of a circuit having a plurality of instance circuit cells of a master circuit cell is provided. Further, a graphical user interface including a user selectable option for an overlay view is provided. In addition, responsive to the selection of the overlay view, the plurality of instance circuit cells of the master circuit cell is determined. In addition, a plurality of sets of circuit elements, each set of circuit elements including external circuit elements that overlap with a corresponding instance circuit cell of the plurality of instance circuit cells is determined. Further, the plurality of sets of circuit elements overlaid on the master circuit cell is displayed on the layout view.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.