Handling surface level coherency without reliance on fencing
US10672366B2 · kind B2 · utility
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11References
4Claims
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Key dates
| Filing date | Jul 15, 2019 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | Jul 15, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2370/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses and methods may provide for technology that detects a memory fence in a thread, adds a group identifier to one or more memory operations in the thread that follow the memory fence, and sends the one or more memory operations and the group identifier to a memory structure. In one example, the group identifier is used to track completion of the one or more memory operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.