Via blocking layer

US10672650B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Rami Hourani · Santa Clara, US
• Marie Krysak · Portland, US
• Florian Gstrein · Portland, US
• Ruth A. Brain · Portland, US
• Mark Bohr · Beaverton, US

Key dates

• Filing date: Feb 18, 2018
• Grant date: Jun 2, 2020
• Expiry date: Feb 18, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2221/1063
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.