Semiconductor device structures including stair step structures, and related semiconductor devices
US10672657B2 · kind B2 · utility
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6References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 27, 2018 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | Jun 14, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device assembly comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate. Portions of the tiers are selectively removed to form a stair step structure comprising a selected number of steps exhibiting different widths corresponding to variances in projected error associated with forming the steps. Contact structures are formed on the steps of the stair step structure. Semiconductor device structures and semiconductor devices are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.