Composite wafer, semiconductor device, electronic component and method of manufacturing a semiconductor device

US10672664B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Paul Ganitzer · Villach, AT
• Carsten von Koblinski · Velden am Wörther See, AT
• Thomas Feil · Villach, AT
• Gerald Lackner · Arnoldstein, AT
• Jochen Mueller · Regensburg, DE
• Martin Poelzl · Ossiach, AT
• Tobias Polster · Villach, AT

Key dates

• Filing date: Feb 27, 2017
• Grant date: Jun 2, 2020
• Expiry date: Feb 27, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/181
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In an embodiment, a method includes forming at least one trench in non-device regions of a first surface of a semiconductor wafer, the non-device regions being arranged between component positions, the component positions including device regions and a first metallization structure, applying a first polymer layer to the first surface of a semiconductor wafer such that the trenches and edge regions of the component positions are covered with the first polymer layer and such that at least a portion of the first metallization structure is uncovered by the first polymer layer, removing portions of a second surface of the semiconductor wafer, the second surface opposing the first surface, revealing portions of the first polymer layer in the non-device regions and producing a worked second surface and inserting a separation line through the first polymer layer in the non-device regions to form a plurality of separate semiconductor dies.