Three-dimensional integrated circuit structure and method of manufacturing the same
US10672737B2 · kind B2 · utility
1Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2018 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | Jan 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06582
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a 3DIC structure includes a wafer, a die and a dielectric layer. The die is over and bonded to the wafer. The dielectric layer is over the wafer and aside the die, covering sidewalls of the die. A total thickness variation (TTV) of the die is less than 0.8 μm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.