Devices and methods of forming low resistivity noble metal interconnect
US10679937B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2017 |
| Grant date | Jun 9, 2020 |
| Priority date | — |
| Expiry date | Oct 17, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5222
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.