Three-dimensional memory device having semiconductor plug formed using backside substrate thinning
US10679985B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2018 |
| Grant date | Jun 9, 2020 |
| Priority date | — |
| Expiry date | Dec 6, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/80905
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending vertically through the memory stack, and a semiconductor layer above the memory stack. The channel structure includes a channel plug in a lower portion of the channel structure, a memory film along a sidewall of the channel structure, and a semiconductor channel over the memory film and in contact with the channel plug. The semiconductor layer includes a semiconductor plug above and in contact with the semiconductor channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.