Ion beam etching fabricated sub 30nm vias to reduce conductive material re-deposition for sub 60nm MRAM devices

US10680168B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Yi Yang · Zhejiang, CN
• Dongna Shen · San Jose, US
• Zhongjian Teng · Santa Clara, US
• Jesmin Haq · Milpitas, US
• Yu-Jen Wang · San Jose, US

Key dates

• Filing date: Apr 6, 2018
• Grant date: Jun 9, 2020
• Expiry date: Apr 28, 2038

Classification

• Technology area (CPC B): Performing Operations; Transporting
• CPC primary: B82Y40/00
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A metal layer and first dielectric hard mask are deposited on a bottom electrode. These are patterned and etched to a first pattern size. The patterned metal layer is trimmed using IBE at an angle of 70-90 degrees wherein the metal layer is reduced to a second pattern size smaller than the first pattern size. A dielectric layer is deposited surrounding the patterned metal layer and polished to expose a top surface of the patterned metal layer to form a via connection to the bottom electrode. A MTJ stack is deposited on the dielectric layer and via connection. The MTJ stack is etched to a pattern size larger than the via size wherein an over etching is performed. Re-deposition material is formed on sidewalls of the dielectric layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.