Jesmin Haq
35Patents
5h-index
15Co-inventors
62Inventor score
Filing activity: May 27, 2011 → Jul 28, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10069064B1 | Memory structure having a magnetic tunnel junction (MTJ) self-aligned to a T-shaped bottom electrode, and method of manufacturing the same | Electricity | 26 | Active |
| US8481859B2 | Method of preparing a flexible substrate assembly and flexible substrate assembly therefrom | Emerging Cross-Sectional Technologies | 16 | Active |
| US8992712B2 | Method for manufacturing electronic devices and electronic devices thereof | Emerging Cross-Sectional Technologies | 12 | Active |
| US9155190B2 | Method of preparing a flexible substrate assembly and flexible substrate assembly therefrom | Emerging Cross-Sectional Technologies | 8 | Active |
| US9972777B1 | MTJ device process/integration method with pre-patterned seed layer | Electricity | 7 | Active |
| US9887350B2 | MTJ etching with improved uniformity and profile by adding passivation step | Electricity | 5 | Active |
| US10103322B1 | Method to remove sidewall damage after MTJ etching | Electricity | 3 | Active |
| US10475991B2 | Fabrication of large height top metal electrode for sub-60nm magnetoresistive random access memory (MRAM) devices | Electricity | 2 | Active |
| US11800811B2 | MTJ CD variation by HM trimming | Electricity | 2 | Active |
| US11430945B2 | MTJ device performance by adding stress modulation layer to MTJ device structure | Physics | 2 | Active |
| US10522751B2 | MTJ CD variation by HM trimming | Electricity | 2 | Active |
| US10446741B2 | Multiple hard mask patterning to fabricate 20nm and below MRAM devices | Electricity | 1 | Active |
| US10854809B2 | STT-MRAM heat sink and magnetic shield structure design for more robust read/write performance | Electricity | 1 | Active |
| US10680168B2 | Ion beam etching fabricated sub 30nm vias to reduce conductive material re-deposition for sub 60nm MRAM devices | Performing Operations; Transporting | 1 | Active |
| US10359699B2 | Self-adaptive halogen treatment to improve photoresist pattern and magnetoresistive random access memory (MRAM) device uniformity | Electricity | 1 | Active |
| US10921707B2 | Self-adaptive halogen treatment to improve photoresist pattern and magnetoresistive random access memory (MRAM) device uniformity | Electricity | 1 | Active |
| US10475987B1 | Method for fabricating a magnetic tunneling junction (MTJ) structure | Physics | 1 | Active |
| US11088320B2 | Fabrication of large height top metal electrode for sub-60nm magnetoresistive random access memory (MRAM) devices | Electricity | 1 | Active |
| US11527711B2 | MTJ device performance by controlling device shape | Electricity | 1 | Active |
| US10944049B2 | MTJ device performance by controlling device shape | Electricity | 1 | Active |
| US10831104B2 | Critical dimension (CD) uniformity of photoresist island patterns using alternating phase shifting mask | Electricity | 0 | Active |
| US11963457B2 | MTJ device performance by controlling device shape | Electricity | 0 | Active |
| US9880473B2 | Surface treatment method for dielectric anti-reflective coating (DARC) to shrink photoresist critical dimension (CD) | Physics | 0 | Active |
| US11217746B2 | Ion beam etching fabricated sub 30nm Vias to reduce conductive material re-deposition for sub 60nm MRAM devices | Performing Operations; Transporting | 0 | Active |
| US11895928B2 | Integration scheme for three terminal spin-orbit-torque (SOT) switching devices | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.