Memory array reset read operation
US10685702B2 · kind B2 · utility
3Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2017 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Aug 28, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2281
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.