Suppression of program disturb with bit line and select gate voltage regulation
US10685724B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2019 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Feb 6, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.