Method of wafer dicing and die
US10685883B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2019 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | May 2, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/5446
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of wafer dicing and a die are provided. The method includes the following processes. A wafer is provided, the wafer includes a plurality of die regions and a scribe region between the die regions. The scribe region includes a substrate, and a dielectric layer and a test structure on the substrate, the test structure is disposed in the dielectric layer. A first removal process is performed to remove the test structure and the dielectric layer around the test structure, so as to expose the substrate. The first removal process includes performing a plurality of etching cycles, and each etching cycle includes performing a first etching process to remove a portion of the test structure and performing a second etching process to remove a portion of the dielectric layer. A second removal process is performed to remove the substrate in the scribe region, so as to form a plurality of dies separated from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.