Adjusting scan event thresholds to mitigate memory errors
US10691377B2 · kind B2 · utility
4Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2018 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | Sep 21, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3422
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.