Layouts for connecting contacts with metal tabs or vias
US10691862B2 · kind B2 · utility
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1References
20Claims
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Assignee
Inventors
Key dates
| Filing date | Jul 7, 2017 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | Apr 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to methodologies for designing semiconductor structures, and, more particularly, creating a methodology to connect contacts of semiconductor elements to a metal line using marker tabs to reserve space for future connections between the contacts and the metal line, and then reassigning the marker tabs to connections between the contacts and the metal line on different levels of a metal stack formed over the semiconductor elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.