Memory structure
US10692875B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2018 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | Nov 1, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
Abstract
A memory structure including a substrate, at least one stacked gate structure, a first spacer conductive layer, and a first contact is provided. The stacked gate structure is located on the substrate and includes a control gate. The control gate extends in a first direction. The first spacer conductive layer is located on one sidewall of the control gate and is electrically insulated from the control gate. The first spacer conductive layer includes a first merged spacer portion and a first non-merged spacer portion. A line width of the first merged spacer portion is greater than a line width of the first non-merged spacer portion. The first contact is connected to the first merged spacer portion. The memory structure can have a larger process window of contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.