Cladding layer epitaxy via template engineering for heterogeneous integration on silicon

US10693008B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Niloy Mukherjee · Beaverton, US
• Marko Radosavljevic · Portland, US
• Jack T. Kavalieros · Portland, US
• Ravi Pillarisetty · Portland, US
• Niti Goel · Portland, US
• Van H. Le · Portland, US
• Gilbert Dewey · Beaverton, US
• Benjamin Chu-Kung · Portland, US

Key dates

• Filing date: Sep 27, 2013
• Grant date: Jun 23, 2020
• Expiry date: Sep 16, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/125
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An apparatus including a semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the semiconductor body including a first material including a first band gap; and a plurality of nanowires including a second material including a second band gap different than the first band gap, the plurality of nanowires disposed in separate planes extending through the first material so that the first material surrounds each of the plurality of nanowires; and a gate stack disposed on the channel region. A method including forming a plurality of nanowires in separate planes above a substrate, each of the plurality of nanowires including a material including a first band gap; individually forming a cladding material around each of the plurality of nanowires, the cladding material including a second band gap; coalescing the cladding material; and disposing a gate stack on the cladding material.