Regulating interface layer formation for two-terminal memory
US10693062B2 · kind B2 · utility
3Cited by
7References
20Claims
0Family size
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Key dates
| Filing date | Dec 6, 2016 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | Dec 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/883
Abstract
Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can be grown on the silicon bearing layer, and the growth of the interface layer can be regulated with N2O plasma.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.