Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface
US10698440B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2018 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | Jan 10, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2272
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A calibration controller determines a latest arriving data strobe at a first data buffer in a read data path between at least one memory chip and a host on a high speed interface. The calibration controller aligns a chip clock distributed to a second data buffer in the read data path with the latest arriving data strobe, wherein data cross a first clock boundary from the first data buffer to the second data buffer, to minimize a latency in the read data path across the first clock boundary. The calibration controller aligns the chip clock with a high speed clock for controlling an unload pointer to unload the data from the second data buffer to a serializer in the read data path, wherein the data cross a second clock boundary from the second data buffer to the serializer, to minimize a latency in the read data path across a second clock boundary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.