Front-end-of-line shape merging cell placement and optimization
US10699050B2 · kind B2 · utility
2Cited by
11References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 3, 2018 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | Sep 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique relates to structuring a semiconductor device. First empty cells are placed against hierarchical boundaries of a macro block. Functional cells are added in the macro block. Remaining areas are filled with second empty cells in the macro block. Shape requirements are determined for the first empty cells and the second empty cells. The first and second empty cells are replaced with determined shape requirements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.