Removal of epitaxy defects in transistors
US10699965B1 · kind B1 · utility
1Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2019 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | Feb 26, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/832
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention are directed to techniques for removing epitaxy defect regions (or nodules) from a semiconductor structure. In a non-limiting embodiment of the invention, a sacrificial gate is formed over a channel region of a fin. The sacrificial gate can include a gate hard mask and a spacer. A source or drain region is formed adjacent to the channel region, resulting in a defect region being formed on a surface of the gate hard mask or the spacer. An organic planarization layer (OPL) is formed on a surface of the source or drain region and the defect region is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.