Inventor · Poughkeepsie, NY, US

Christopher M. Prindle

20Patents
7h-index
33Co-inventors
65Inventor score

Filing activity: Aug 27, 2003 → Feb 26, 2019

Most-cited inventions

PatentTitleAreaCited byStatus
US9147748B1 Methods of forming replacement spacer structures on semiconductor devices Electricity 24 Active
US10388770B1 Gate and source/drain contact structures positioned above an active region of a transistor device Electricity 24 Active
US10388747B1 Gate contact structure positioned above an active region with air gaps positioned adjacent the gate structure Electricity 15 Active
US6924232B2 Semiconductor process and composition for forming a barrier material overlying copper Electricity 15 Expired
US9640533B2 Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression Electricity 13 Active
US7601641B1 Two step optical planarizing layer etch Electricity 8 Active
US9236452B2 Raised source/drain EPI with suppressed lateral EPI overgrowth Electricity 7 Active
US8748302B2 Replacement gate approach for high-k metal gate stacks by using a multi-layer contact level Electricity 6 Active
US8735236B2 High-k metal gate electrode structure formed by removing a work function on sidewalls in replacement gate technology Electricity 5 Active
US9876077B1 Methods of forming a protection layer on an isolation region of IC products comprising FinFET devices Electricity 5 Active
US9184263B2 Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices Electricity 5 Active
US9806078B1 FinFET spacer formation on gate sidewalls, between the channel and source/drain regions Electricity 3 Active
US9230802B2 Transistor(s) with different source/drain channel junction characteristics, and methods of fabrication Electricity 2 Active
US10734525B2 Gate-all-around transistor with spacer support and methods of forming same Electricity 2 Active
US10699965B1 Removal of epitaxy defects in transistors Electricity 1 Active
US10170544B2 Integrated circuit products that include FinFET devices and a protection layer formed on an isolation region Electricity 1 Active
US9496354B2 Semiconductor devices with dummy gate structures partially on isolation regions Electricity 1 Active
US10290738B2 Methods of forming epi semiconductor material on a recessed fin in the source/drain regions of a FinFET device Electricity 0 Active
US9685384B1 Devices and methods of forming epi for aggressive gate pitch Electricity 0 Active
US10068978B2 Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.