Memory system with decoders and method of operating such memory system and decoders
US10700706B2 · kind B2 · utility
7Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Sep 11, 2018 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | Oct 17, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system, a controller including a bit-flipping (BF) decoder and a min-sum (MS) decoder that may be included in the memory system and operating methods thereof in which the controller determines a quality metric as a function of initial syndrome weight and information of the BF decoder after a set number of decoding iterations by the BF decoder in a test period. After the test period, the controller applies the quality metric to each codeword to determine whether to send that codeword first to the BF decoder for decoding or directly to the MS decoder for decoding.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.