Coherency directory entry allocation based on eviction costs
US10705958B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2018 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Jan 1, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6046
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor partitions a coherency directory into different regions for different processor cores and manages the number of entries allocated to each region based at least in part on monitored recall costs indicating expected resource costs for reallocating entries. Examples of monitored recall costs include a number of cache evictions associated with entry reallocation, the hit rate of each region of the coherency directory, and the like, or a combination thereof. By managing the entries allocated to each region based on the monitored recall costs, the processor ensures that processor cores associated with denser memory access patterns (that is, memory access patterns that more frequently access cache lines associated with the same memory pages) are assigned more entries of the coherency directory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.