Wafer level flat no-lead semiconductor packages and methods of manufacture
US10707111B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2019 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Mar 5, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.