Solid state memory device, and manufacturing method thereof

US10707121B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Jun Liu · Shanghai, CN
• Mark A. Levan · Boise, US
• Gordon A. Haller · Boise, US
• Fei Wang · Beijing, CN
• Wei Yeeng Ng · Boise, US
• Wesley O. McKinsey · Nampa, US
• Zhiqiang Xie · Fuzhou, CN
• Jeremy Adams · Boise, US
• Hongbin Zhu · Boise, US
• Jun Zhao · Mianyang, CN

Key dates

• Filing date: Dec 31, 2016
• Grant date: Jul 7, 2020
• Expiry date: Dec 31, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/27
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Conductive structure technology is disclosed. In one example, a conductive structure can include an interconnect and a plurality of conductive layers overlying the interconnect. Each conductive layer can be separated from an adjacent conductive layer by an insulative layer. In addition, the conductive structure can include a contact extending through the plurality of conductive layers to the interconnect. The contact can be electrically coupled to the interconnect and insulated from the plurality of conductive layers. Associated systems and methods are also disclosed.