Integrated circuitry comprising an array, method of forming an array, method of forming DRAM circuitry, and method used in the fabrication of integrated circuitry

US10707211B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Cornel Bozdog · Boise, US
• Abhilasha Bhardwaj · Boise, US
• Byeung Chul Kim · Boise, US
• Michael E. Koltonski · Boise, US
• Gurtej S. Sandhu · Boise, US
• Matthew Thorum · Boise, US

Key dates

• Filing date: Sep 24, 2018
• Grant date: Jul 7, 2020
• Expiry date: Sep 24, 2038

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/908
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Integrated circuitry comprising an array comprises a plurality of conductive vias. Individual of the vias comprise an upper horizontal perimeter comprising opposing end portions. One of the opposing end portions comprises opposing straight sidewalls. The other of the opposing end portions comprises opposing curved sidewalls that join with the opposing straight sidewalls of the one opposing end portion. Other embodiments, including methods, are disclosed.