Matthew Thorum
25Patents
3h-index
27Co-inventors
55Inventor score
Filing activity: Apr 24, 2013 → Feb 23, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9435049B2 | Alkaline pretreatment for electroplating | Chemistry; Metallurgy | 8 | Active |
| US9617648B2 | Pretreatment of nickel and cobalt liners for electrodeposition of copper into through silicon vias | Electricity | 5 | Active |
| US9689083B2 | TSV bath evaluation using field versus feature contrast | Electricity | 3 | Active |
| US10957530B2 | Freezing a sacrificial material in forming a semiconductor | Performing Operations; Transporting | 1 | Active |
| US10508359B2 | TSV bath evaluation using field versus feature contrast | Electricity | 1 | Active |
| US10094038B2 | Monitoring electrolytes during electroplating | Chemistry; Metallurgy | 1 | Active |
| US10475656B2 | Hydrosilylation in semiconductor processing | Electricity | 1 | Active |
| US9816196B2 | Method and apparatus for electroplating semiconductor wafer when controlling cations in electrolyte | Chemistry; Metallurgy | 1 | Active |
| US10784101B2 | Using sacrificial solids in semiconductor processing | Electricity | 1 | Active |
| US11037779B2 | Gas residue removal | Performing Operations; Transporting | 0 | Active |
| US10707211B2 | Integrated circuitry comprising an array, method of forming an array, method of forming DRAM circuitry, and method used in the fabrication of integrated circuitry | Emerging Cross-Sectional Technologies | 0 | Active |
| US10937644B2 | Using sacrificial solids in semiconductor processing | Electricity | 0 | Active |
| US12237013B2 | Integrated assemblies and methods of forming integrated assemblies | Electricity | 0 | Active |
| US10964525B2 | Removing a sacrificial material via sublimation in forming a semiconductor | Performing Operations; Transporting | 0 | Active |
| US11482409B2 | Freezing a sacrificial material in forming a semiconductor | Performing Operations; Transporting | 0 | Active |
| US11495610B2 | Integrated circuitry, a method used in forming integrated circuitry, and a method used in forming a memory array comprising strings of memory cells | Electricity | 0 | Active |
| US10825686B2 | Hydrosilylation in semiconductor processing | Electricity | 0 | Active |
| US12041779B2 | Integrated assemblies and methods of forming integrated assemblies | Electricity | 0 | Active |
| US11791152B2 | Residue removal during semiconductor device formation | Performing Operations; Transporting | 0 | Active |
| US11296103B2 | Integrated assemblies and methods of forming integrated assemblies | Electricity | 0 | Active |
| US11600485B2 | Using sacrificial solids in semiconductor processing | Electricity | 0 | Active |
| US12191249B2 | Microelectronic devices including staircase structures, and related memory devices, electronic systems, and methods | Physics | 0 | Active |
| US12322585B2 | Sublimation in forming a semiconductor | Performing Operations; Transporting | 0 | Active |
| US10774438B2 | Monitoring electrolytes during electroplating | Chemistry; Metallurgy | 0 | Active |
| US10943907B2 | Integrated circuitry comprising an array, method of forming an array, method of forming DRAM circuitry, and method used in the fabrication of integrated circuitry | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.