Method, apparatus, and system for improving scaling of isolation structures for gate, source, and/or drain contacts
US10707303B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2019 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Jan 31, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device, comprising a semiconductor substrate; an isolation layer disposed on the semiconductor substrate; a first active region and a second active region disposed at least partially above the isolation layer; a first gate structure and a second gate structure disposed on the isolation layer, the first active region, and the second active region; and an isolation pillar disposed on the isolation layer, between the first and second active regions, and between and in contact with the first and second gate structures, wherein the isolation pillar has an inverted-T shape. A method for making the semiconductor device. A system configured to implement the method and manufacture the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.