Surround gate vertical field effect transistors including tubular and strip electrodes and method of making the same
US10707314B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2017 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Oct 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/823
Abstract
A stack including doped semiconductor strips, a one-dimensional array of gate electrode strips, and a dielectric matrix layer is formed over a substrate. A two-dimensional array of openings is formed through the dielectric matrix layer and the one-dimensional array of gate electrode strips. A two-dimensional array of tubular gate electrode portions is formed in the two-dimensional array of openings. Each of the tubular gate electrode portions is formed directly on a respective one of the gate electrode strips. Gate dielectrics are formed on inner sidewalls of the tubular gate electrode portions. Vertical semiconductor channels are formed within each of the gate dielectrics by deposition of a semiconductor material. A two-dimensional array of vertical field effect transistors including surrounding gate electrodes is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.