Bit-flipping decoder for G-LDPC codes with syndrome-decoding for component codes
US10707899B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2018 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Mar 9, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1111
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques are described for performing a bit-flipping decoding scheme on a G-LDPC codeword. In an example, a decoding system uses two syndrome tables. The first syndrome table identifies a predefined syndrome for a component codeword that protects a bit of the G-LDPC codeword. This predefined syndrome is identified based on a location of the bit and is used to update a current syndrome of the component codeword. The second syndrome table identifies one or more bit error locations for the component codeword. The bit error locations are identified from the second syndrome table based on the current syndrome of the component codeword, as updated. In an example, the error locations are used to update a reliability of the bit if its location corresponds to one of the error locations. A bit flipping decision is made for the bit based on its reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.