Integrated circuit design system with automatic timing margin reduction
US10713409B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2019 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | Mar 12, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) device is disclosed. The IC device includes a global clock source to generate a global clock signal. Multiple local clock sources are employed in the IC device. Each local clock source provides a local clock signal for a partitioned sub-design block in the IC device. Each local clock signal is based on the global clock signal. The IC device includes a clock controller having inputs from the global clock source and the multiple local clock sources. The clock controller (1) measures skew between each local clock source and the global clock source, and (2) generates respective control signals to adjust respective phases of each local clock signal to reduce the measured skew.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.