Memory system capable of pre-screening internal transistors
US10714201B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2019 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | Sep 17, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a plurality of memory cells. A memory cell includes an anti-fuse transistor, a first select unit, and a second select unit. The anti-fuse transistor has a first terminal, a second terminal, and a control terminal coupled to an anti-fuse control line. The first select unit is coupled to the first terminal of the anti-fuse transistor, a first bit line, and an odd word line. The second select unit is coupled to the second terminal of the anti-fuse transistor, a second bit line, and an even word line. During a pre-screen operation of the memory cell, the odd word line and the even word line are at different voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.