Method for controlling transistor delay of nanowire or nanosheet transistor devices
US10714391B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2018 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | Nov 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device includes: providing a substrate including a first stacked fin structure for forming a channel of a first gate-all-around (GAA) transistor, the first stacked fin structure including an initial volume of first channel material, and a second stacked fin structure for forming a channel of a second GAA transistor, the second stacked fin structure including an initial volume of second channel material; reducing said initial volume of the second channel material relative to the initial volume of first channel material by a predetermined amount corresponding to a delay of the first GAA transistor; and forming first and second GAA gate structures around said first channel material and said second channel material respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.