Inventor · Boise, ID, US

Anton J. deVilliers

200Patents

12h-index

75Co-inventors

85Inventor score

Filing activity: May 22, 2008 → Jul 18, 2023

Most-cited inventions

Patent	Title	Area	Cited by	Status
US10586765B2	Buried power rails	Electricity	31	Active
US9837314B2	Self-alignment of metal and via using selective deposition	Electricity	23	Active
US8629048B1	Methods of forming a pattern on a substrate	Electricity	22	Active
US9997598B2	Three-dimensional semiconductor device and method of fabrication	Electricity	21	Active
US10453850B2	Three-dimensional semiconductor device including integrated circuit, transistors and transistor components and method of fabrication	Electricity	19	Active
US10388519B2	Method and device for incorporating single diffusion break into nanochannel structures of FET devices	Electricity	18	Active
US8273634B2	Methods of fabricating substrates	Electricity	18	Active
US8247302B2	Methods of fabricating substrates	Electricity	17	Active
US10833078B2	Semiconductor apparatus having stacked gates and method of manufacture thereof	Electricity	16	Active
US8796155B2	Methods of fabricating substrates	Electricity	16	Active
US8492282B2	Methods of forming a masking pattern for integrated circuits	Electricity	13	Active
US8575032B2	Methods of forming a pattern on a substrate	Electricity	13	Active
US10573655B2	Three-dimensional semiconductor device and method of fabrication	Electricity	12	Active
US8871646B2	Methods of forming a masking pattern for integrated circuits	Electricity	12	Active
US10529830B2	Extension region for a semiconductor device	Electricity	12	Active
US10734224B2	Method and device for incorporating single diffusion break into nanochannel structures of FET devices	Electricity	11	Active
US9645495B2	Critical dimension control in photo-sensitized chemically-amplified resist	Physics	10	Active
US10770479B2	Three-dimensional device and method of forming the same	Electricity	9	Active
US9240329B2	Method for multiplying pattern density by crossing multiple patterned layers	Electricity	9	Active
US10622233B2	Amelioration of global wafer distortion based on determination of localized distortions of a semiconductor wafer	Physics	8	Active
US10714391B2	Method for controlling transistor delay of nanowire or nanosheet transistor devices	Electricity	8	Active
US9718082B2	Inline dispense capacitor	Emerging Cross-Sectional Technologies	8	Active
US9818611B2	Methods of forming etch masks for sub-resolution substrate patterning	Electricity	8	Active
US8815752B2	Methods of forming features in semiconductor device structures	Electricity	8	Active
US8288083B2	Methods of forming patterned masks	Electricity	7	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.