Anti-fuse with self aligned via patterning
US10714422B2 · kind B2 · utility
1Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2018 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | Oct 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5226
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to semiconductor structures and, more particularly, to an anti-fuse with self-aligned via patterning and methods of manufacture. The anti-fuse includes: a lower wiring layer composed of a plurality of lower wiring structures; at least one via structure in direct contact and misaligned with a first wiring structure of the plurality of lower wiring structures and offset from a second wiring structure of the plurality of lower wiring structures; and an upper wiring layer composed of at least one upper wiring structure in direct contact with the at least one via structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.