3D memory device with silicon nitride and buffer oxide layers and method of manufacturing the same
US10714494B2 · kind B2 · utility
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4References
19Claims
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Key dates
| Filing date | Nov 23, 2017 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | Nov 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a memory device including a substrate, a stack layer, a channel structure, a charge storage structure, a silicon nitride layer, and a buffer oxide layer. The stack layer is disposed over the substrate. The stack layer includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The channel structure penetrates through the stack layer. The charge storage structure surrounds a sidewall of the channel structure. The silicon nitride layer surrounds the conductive layers. The buffer oxide layer is disposed between the conductive layers and the silicon nitride layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.